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LTC3891 1 3891fa typical application features description low i q , 60v synchronous step-down controller the ltc ? 3891 is a high performance step-down switching regulator dc/dc controller that drives an all n-channel synchronous power mosfet stage. a constant fre - quency current mode architecture allows a phase-lockable frequency of up to 750khz. the 50a no-load quiescent current extends operating run time in battery-powered systems. opti-loop ? compensa - tion allows the transient response to be optimized over a wide range of output capacitance and esr values. the LTC3891 features a precision 0.8v reference and power good output indicator. a wide 4v to 60v input supply range encompasses a wide range of intermediate bus voltages and battery chemistries. the output voltage of the LTC3891 can be programmed between 0.8v to 24v. the track/ss pin ramps the output voltages during start-up. current foldback limits mosfet heat dissipation during short-circuit conditions. the pllin/mode pin se - lects among burst mode operation, pulse-skipping mode, or continuous conduction mode at light loads. efficiency and power loss vs output current applications n wide v in range: 4v to 60v (65v abs max) n low operating i q : 50a n wide output voltage range: 0.8v v out 24v n r sense or dcr current sensing n phase-lockable frequency (75khz to 750khz) n programmable fixed frequency (50khz to 900khz) n selectable continuous, pulse-skipping or low ripple burst mode ? operation at light load n selectable current limit n very low dropout operation: 99% duty cycle n adjustable output voltage soft-start or tracking n power good output voltage monitor n output overvoltage protection n low shutdown i q : < 14a n internal ldo powers gate drive from v in or extv cc n no current foldback during start-up n small 20-pin 3mm 4mm qfn and tssop packages n automotive always-on systems n battery powered digital devices n distributed dc power systems l , lt, ltc, ltm, opti-loop, burst mode, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patents, including 5481178, 5705919, 6611131, 6498466, 6580258, 7230497. 0.1f 22f v in 4v to 60v 41.2k 10k 2200pf 100k 31.6k 3891 ta01a 2.2f 100pf 0.1f freq ith sgnd LTC3891 v in intv cc 4.7h 8m intv cc boost sw bg sense + sense ? tg 100k 150f v out 3.3v 5a track/ss v fb pgood output current (a) 0 efficiency (%) power loss (mw) 70 100 10.1 0.01 0.001 0.0001 10 3891 ta01b 50 40 30 20 1 10 100 1000 10000 0.1 10 60 80 90 v in = 12v v out = 3.3v high efficiency 3.3v step-down converter
LTC3891 2 3891fa pin configuration absolute maximum ratings input supply voltage (v in ) ......................... C0.3v to 65v topside driver voltage (boost) ................. C0.3v to 71v switch voltage (sw) ..................................... C5v to 65v (boost-sw) ................................................ C0.3v to 6v run ............................................................. C0.3v to 8v maximum current sourced into pin from source > 8v ...................................................... 100a sense + , sense C voltages ......................... C0.3v to 28v pllin/mode, intv cc voltages ................... C0.3v to 6v i lim , freq voltages .............................. C0.3v to intv cc extv cc ...................................................... C0.3v to 14v (note 1) 20 19 18 17 7 8 top view 21 sgnd udc package 20-lead (3mm 4mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 pllin/mode sgnd sgnd run sense ? sense + pgnd extv cc intv cc bg boost sw freq track/ss i lim v in v fb ith pgood tg t jmax = 150c, ja = 43c/w exposed pad (pin 21) is sgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 track/ss freq pllin/mode sgnd sgnd run sense ? sense + v fb ith i lim v in pgnd extv cc intv cc bg boost sw tg pgood 21 sgnd fe package 20-lead plastic tssop t jmax = 150c, ja = 38c/w exposed pad (pin 21) is sgnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range LTC3891eudc#pbf LTC3891eudc#trpbf lfxv 20-lead (3mm 4mm) plastic qfn C40c to 125c LTC3891iudc#pbf LTC3891iudc#trpbf lfxv 20-lead (3mm 4mm) plastic qfn C40c to 125c LTC3891hudc#pbf LTC3891hudc#trpbf lfxv 20-lead (3mm 4mm) plastic qfn C40c to 150c LTC3891mpudc#pbf LTC3891mpudc#trpbf lfxv 20-lead (3mm 4mm) plastic qfn C55c to 150c ith, v fb voltages ......................................... C0.3v to 6v pgood voltage ............................................ C0.3v to 6v track/ss voltage ....................................... C0.3v to 6v operating junction temperature range (notes 2, 3) LTC3891e, LTC3891i .......................... C40c to 125c LTC3891h .......................................... C40c to 150c LTC3891mp ....................................... C55c to 150c maximum junction temperature (notes 2, 3) LTC3891e, LTC3891i ......................................... 125c LTC3891h, LTC3891mp .................................... 150c storage temperature range .................. C65c to 150c
LTC3891 3 3891fa the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2), v in = 12v, v run = 5v, extv cc = 0v unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v in input supply operating voltage range 4 60 v v fb regulated feedback voltage (note 4); i th voltage = 1.2v C40c to 85c LTC3891e, LTC3891i LTC3891h, LTC3891mp l l 0.792 0.788 0.786 0.800 0.800 0.800 0.808 0.812 0.812 v v v i fb feedback current (note 4) 5 50 na v reflnreg reference voltage line regulation (note 4); v in = 4.5v to 60v 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; ?i th voltage = 1.2v to 0.7v l 0.01 0.1 % (note 4) measured in servo loop; ?i th voltage = 1.2v to 2v l C0.01 C0.1 % g m transconductance amplifier g m (note 4); i th = 1.2v; sink/source 5a 2 mmho i q input dc supply current (note 5) pulse skip or forced continuous mode v fb = 0.83v (no load) 2 ma sleep mode v fb = 0.83v (no load) 50 75 a shutdown run = 0v 14 25 a uvlo undervoltage lockout intv cc ramping up intv cc ramping down l l 3.6 3.92 3.80 4.2 4.0 v v v ovl feedback overvoltage protection measured at v fb relative to regulated v fb 7 10 13 % i sense + sense + pin current 1 a i sense C sense C pins current v sense C < intv cc C 0.5v v sense C > intv cc + 0.5v 700 2 a a df max maximum duty factor in dropout 98 99 % i track/ss soft-start charge current v track = 0v 7 10 14 a v run on run pin on threshold v run rising l 1.15 1.21 1.27 v v run hyst run pin hysteresis 50 mv v sense(max) maximum current sense threshold v fb = 0.7v, v sense C = 3.3v, i lim = 0 v fb = 0.7v, v sense C = 3.3v, i lim = intv cc v fb = 0.7v, v sense C = 3.3v, i lim = float l l l 22 43 64 30 50 75 36 57 85 mv mv mv order information lead free finish tape and reel part marking* package description temperature range LTC3891efe#pbf LTC3891efe#trpbf LTC3891fe 20-lead plastic tssop C40c to 125c LTC3891ife#pbf LTC3891ife#trpbf LTC3891fe 20-lead plastic tssop C40c to 125c LTC3891hfe#pbf LTC3891hfe#trpbf LTC3891fe 20-lead plastic tssop C40c to 150c LTC3891mpfe#pbf LTC3891mpfe#trpbf LTC3891fe 20-lead plastic tssop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC3891 4 3891fa electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c (note 2), v in = 12v, v run = 5v, extv cc = 0v unless otherwise noted. symbol parameter conditions min typ max units gate driver tg pull-up on-resistance pull-down on-resistance 2.5 1.5 bg pull-up on-resistance pull-down on-resistance 2.4 1.1 tg t r tg t f tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 16 ns ns bg t r bg t f bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 13 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf 30 ns bg/tg t 1d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf 30 ns t on(min) minimum on-time (note 7) 95 ns intv cc linear regulator v intvccvin internal v cc voltage 6v < v in < 60v, v extvcc = 0v 4.85 5.1 5.35 v v ldovin intv cc load regulation i cc = 0ma to 50ma, v extvcc = 0v 0.7 1.1 % v intvccext internal v cc voltage 6v < v extvcc < 13v 4.85 5.1 5.35 v v ldoext intv cc load regulation i cc = 0ma to 50ma, v extvcc = 8.5v 0.6 1.1 % v extvcc extv cc switchover voltage i cc = 0ma to 50ma, extv cc ramping positive 4.5 4.7 4.9 v v ldohys extv cc hysteresis 250 mv oscillator and phase-locked loop f 25k programmable frequency r freq = 25k; pllin/mode = dc voltage 105 khz f 65k programmable frequency r freq = 65k; pllin/mode = dc voltage 375 440 505 khz f 105k programmable frequency r freq =105k; pllin/mode = dc voltage 835 khz f low low fixed frequency v freq = 0v; pllin/mode = dc voltage 320 350 380 khz f high high fixed frequency v freq = intv cc ; pllin/mode = dc voltage 485 535 585 khz f sync synchronizable frequency pllin/mode = external clock l 75 750 khz pgood1 output v pgl pgood voltage low i pgood = 2ma 0.2 0.4 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative C13 C10 C7 % hysteresis 2.5 % v fb ramping positive 7 10 13 % hysteresis 2.5 % t pg delay for reporting a fault 25 s
LTC3891 5 3891fa typical performance characteristics output current (a) figure 12 circuit 0 efficiency (%) power loss (mw) 70 100 10.1 0.01 0.001 0.0001 10 3891 g01 50 40 30 20 1 10 100 1000 10000 0.1 10 60 80 90 v in = 12v v out = 3.3v burst efficiency fcm loss pulse-skipping loss burst loss fcm efficiency pulse-skipping efficiency output current (a) 0 efficiency (%) 70 100 10.1 0.01 0.001 0.0001 10 3891 g02 50 40 30 20 10 60 80 90 v out = 8.5v v out = 3.3v v in = 12v burst mode operation figures 12, 14 circuits input voltage (v) 80 efficiency (%) 94 100 20 30 35 40 45 50 55 60 151050 25 3891 g03 90 88 86 84 82 92 96 98 v out = 3.3v v out = 8.5v i load = 2a figures 12, 14 circuits efficiency and power loss vs output current efficiency vs output current efficiency vs input voltage note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3891 is tested under pulsed load conditions such that t j t a . the LTC3891e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3891i is guaranteed over the C40c to 125c operating junction temperature range, the LTC3891h is guaranteed over the C40c to 150c operating junction temperature range and the LTC3891mp is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ), where ja is 43c/w for the qfn or 38c/w for the tssop. note 4: the LTC3891 is tested in a feedback loop that servos v ith to a specified voltage and measures the resultant v fb . the specification at 85c is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125c for the LTC3891e/LTC3891i, 150c for the LTC3891h/LTC3891mp). for the LTC3891mp, the specification at C40c is not tested in production and is assured by design, characterization and correlation to production testing at C55c. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). electrical characteristics
LTC3891 6 3891fa typical performance characteristics input voltage (v) 0 supply current (a) 200 300 20 30 35 40 45 50 55 60 65 15105 25 3891 g10 150 100 50 250 no load 300a load figure 12 circuit temperature (c) ?75 4.0 extv cc and intv cc voltage (v) 4.2 4.6 4.8 5.0 6.0 5.4 ?25 25 50 75 100 3891 g11 4.4 5.6 5.8 5.2 ?50 0 125 150 intv cc extv cc rising extv cc falling total input supply current vs input voltage extv cc switchover and intv cc voltages vs temperature intv cc line regulation v in = 12v v out = 3.3v i load = 200a 5s/div 3891 g07 forced continuous mode pulse-skipping mode burst mode operation 1a/div inductor current at light load soft start-up tracking start-up figures 12, 14 circuits 2ms/div 3891 g08 v out = 3.3v 2v/div v out = 8.5v 2v/div 2ms/div 3891 g09 v out 2v/div master 2v/div input voltage (v) 3.0 intv cc voltage (v) 4.0 4.5 5.5 20 30 35 40 45 50 55 60 65 15100 5 25 3891 g12 3.5 5.0 i load = 10ma load step burst mode operation load step forced continuous mode load step pulse-skipping mode load step = 100ma to 3a v in = 12v v out = 3.3v figure 12 circuit 50s/div 3891 g04 v out 100mv/div ac- coupled i l 2a/div load step = 100ma to 3a v in = 12v v out = 3.3v figure 12 circuit 50s/div 3891 g05 v out 100mv/div ac- coupled i l 2a/div load step = 100ma to 3a v in = 12v v out = 3.3v figure 12 circuit 50s/div 3891 g06 v out 100mv/div ac- coupled i l 2a/div
LTC3891 7 3891fa typical performance characteristics v ith (v) 0 current sense theshold (mv) 40 60 80 0.6 1.0 3891 g13 20 0 0.2 0.4 0.8 1.2 1.4 ?20 ?40 burst mode operation pulse-skipping mode 5% duty cycle forced continuous mode i lim = float i lim = intv cc i lim = gnd v sense common mode voltage (v) 0 sense ? current (a) 20 3891 g14 400 300 10 15 5 25 800 700 600 500 200 100 0 ?100 duty cycle (%) 0 maximum current sense voltage (mv) 50 40 60 70 80 3891 g15 30 20 20 40 50 100 80 60 10 30 90 70 i lim = float i lim = intv cc i lim = gnd feedback voltage (mv) 0 maximum current sense voltage (mv) 40 60 800 3891 g16 20 0 200 400 500 80 30 50 10 70 600 100 300 700 i lim = float i lim = intv cc i lim = gnd temperature (c) ?75 quiescent current (a) 75 50250 3891 g17 60 50 ?50 ?25 75 45 30 40 35 80 70 65 55 100 125 150 v in = 12v maximum current sense voltage vs i th voltage sense C pin input bias current maximum current sense threshold vs duty cycle foldback current limit quiescent current vs temperature intv cc vs load current temperature (c) ?75 regulated feedback voltage (mv) 806 0 25 50 3891 g21 800 796 ?50 ?25 75 794 792 808 804 802 798 100 125 150 track/ss pull-up current vs temperature shutdown (run) threshold vs temperature regulated feedback voltage vs temperature load current (ma) 0 intv cc voltage (v) 5.25 40 3891 g18 4.50 20 60 4.00 5.50 5.00 4.75 4.25 80 100 extv cc = 5v extv cc = 8.5v extv cc = 0v v in = 12v temperature (c) ?75 track/ss current (a) 11.5 5025 3891 g19 10.0 ?25 0 ?50 75 12.0 11.0 10.5 9.5 9.0 8.5 8.0 125100 150 temperature (c) ?75 run pin voltage (v) 500 25 3891 g20 1.20 ?25?50 75 1.30 1.25 1.15 1.10 125100 150 run rising run falling
LTC3891 8 3891fa temperature (c) ?75 intv cc voltage (v) 3.7 3.8 3.9 4.1 ?25 75 100 3891 g25 3.6 4.2 4.0 ?50 0 25 50 125 150 falling rising input voltage (v) 344 oscillator frequency (khz) 348 350 356 20 30 35 40 45 50 55 60 65 15105 25 3891 g26 346 352 354 freq = gnd temperature (c) 8 shutdown current (a) 12 14 22 20 25 50 75 100 125 150 ?25 ?75 ?50 0 3891 g27 10 16 18 v in = 12v undervoltage lockout threshold vs temperature oscillator frequency vs input voltage shutdown current vs temperature typical performance characteristics input voltage (v) 0 shutdown current (a) 10 15 30 25 20 30 35 40 45 50 55 60 65 15105 25 3891 g23 5 20 temperature (c) ?75 frequency (khz) 500 550 600 0 25 50 100 3891 g24 450 400 ?50 ?25 75 125 150 350 300 freq = gnd freq = intv cc sense C pin input bias current vs temperature shutdown current vs input voltage oscillator frequency vs temperature temperature (c) ?75 sense ? current (a) 50250 3891 g22 400 300 ?25?50 75 800 700 600 500 200 100 0 ?100 125100 150 v out > intv cc + 0.5v v out < intv cc ? 0.5v
LTC3891 9 3891fa pin functions pllin/mode (pin 1/pin 3): external synchronization input to phase detector and forced continuous mode input. when an external clock is applied to this pin, the phase-locked loop will force the rising tg signal to be synchronized with the rising edge of the external clock, and the regulator operates in forced continuous mode. when not synchronizing to an external clock, this input determines how the LTC3891 operates at light loads. pull - ing this pin to ground selects burst mode operation. an internal 100k resistor to ground also invokes burst mode operation when the pin is floated. tying this pin to intv cc forces continuous inductor current operation. tying this pin to a voltage greater than 1.2v and less than intv cc C1.3v selects pulse-skipping operation. sgnd (pins 2, 3, exposed pad pin 21/pins 4, 5, exposed pad pin 21): small-signal ground, must be routed separately from high current grounds to the common (C) terminals of the c in capacitor. pins 2, 3/4, 5, must both be electrically connected to small signal ground for proper operation.the exposed pad must be soldered to pcb ground for rated thermal performance. run (pin 4/pin 6): digital run control input. forcing this pin below 1.16v shuts down the controller. forcing this pin below 0.7v shuts down the entire LTC3891, reducing quiescent current to approximately 14a. sense C (pin 5/pin 7): the (C) input to the differential current comparator. when greater than intv cc C 0.5v, the sense C pin supplies power to the current comparator. sense + (pin 6/pin 8): the (+) input to the differential current comparator is normally connected to dcr sensing network or current sensing resistor. the ith pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold. v fb (pin 7/pin 9): receives the remotely sensed feed - back voltage from an external resistive divider across the output. ith (pin 8/pin 10): error amplifier outputs and switching regulator compensation point. the current comparator trip point increases with this control voltage. pgood (pin 9/pin 11): open-drain logic output. pgood is pulled to ground when the voltage on the v fb pin is not within 10% of its set point. tg (pin 10/pin 12): high current gate drives for top n-channel mosfet. this is the output of floating driver with a voltage swing equal to intv cc superimposed on the switch node voltage sw. sw (pin 11/ pin 13): switch node connection to induc - tor. boost (pin 12/pin 14): bootstrapped supply to the top- side floating driver. a capacitor is connected between the boost and sw pin and a schottky diode is tied between the boost and intv cc pins. voltage swing at the boost pin is from intv cc to (v in + intv cc ). bg (pin 13/pin 15): high current gate drive for bottom (synchronous) n-channel mosfet. voltage swing at this pin is from ground to intv cc . intv cc (pin 14/pin 16): output of the internal linear low dropout regulator. the driver and control circuits are powered from this voltage source. must be decoupled to pgnd with a minimum of 2.2f ceramic or other low esr capacitor. do not use the intv cc pin for any other purpose. extv cc (pin 15/pin 17): external power input to an internal ldo connected to intv cc . this ldo supplies intv cc power, bypassing the internal ldo powered from v in whenever extv cc is higher than 4.7v. see extv cc connection in the applications information section. do not float or exceed 14v on this pin. pgnd (pin 16/pin 18): driver power ground. connects to the source of bottom (synchronous) n-channel mosfet and the (C) terminal of c in . v in (pin 17/pin 19): main supply pin. a bypass capacitor should be tied between this pin and the sgnd pins. i lim (pin 18/pin 20): current comparator sense voltage range inputs. tying this pin to sgnd, float or intv cc sets the maximum current sense threshold to one of three different levels for the comparator. (qfn/etssop)
LTC3891 10 3891fa functional diagram pin functions track/ss (pin 19/pin 1): external tracking and soft- start input. the LTC3891 regulates the v fb voltage to the smaller of 0.8v or the voltage on the track/ss pin. an internal 10a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to final regulated output voltage. alternatively, a resistor divider on another voltage supply connected to this pin allows the LTC3891 output to track another supply during start-up. sw top boost tg c b c in d d b pgnd bot bg intv cc intv cc v in c out v out 3891 fd r sense drop out det bot top on s r q q shdn sleep 0.425v icmp 2.7v 0.65v ir 2mv slope comp sense + sense ? pgood v fb 0.88v 0.72v l + ? + ? freq + ? + ? + ? + ? + ? + ? switch logic v fb r a c c r c c c2 r b 0.80v track/ss 0.88v 7a 11v run ith track/ss + ? c ss 10a shdn current limit foldback shdn rst 2(v fb ) pllin/mode 20a vco ldo en intv cc 5.1v sync det 100k clk2 clk1 i lim v in extv cc ldo pfd en 4.7v 5.1v + ? sgnd ea ov freq (pin 20/pin 2): the frequency control pin for the internal vco. connecting the pin to gnd forces the vco to a fixed low frequency of 350khz. connecting the pin to intv cc forces the vco to a fixed high frequency of 535khz. other frequencies between 50khz and 900khz can be programmed by using a resistor between freq and gnd. an internal 20a pull-up current develops the voltage to be used by the vco to control the frequency.
LTC3891 11 3891fa operation main control loop the LTC3891 uses a constant frequency, current mode step-down architecture. during normal operation, the external top mosfet is turned on when the clock for that channel sets the rs latch, and is turned off when the main current comparator, icmp, resets the rs latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the ith pin, which is the output of the error amplifier, ea. the error amplifier compares the output voltage feedback signal at the v fb pin (which is generated with an external resistor divider connected across the output voltage, v out , to ground) to the internal 0.800v reference voltage. when the load cur - rent increases, it causes a slight decrease in v fb relative to the reference, which causes the ea to increase the ith voltage until the average inductor current matches the new load current. after the top mosfet is turned off each cycle, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the current comparator ir, or the beginning of the next clock cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is tied to a voltage less than 4.7v, the v in ldo (low dropout linear regulator) supplies 5.1v from v in to intv cc . if extv cc is taken above 4.7v, the v in ldo is turned off and an extv cc ldo is turned on. once enabled, the extv cc ldo supplies 5.1v from extv cc to intv cc . using the extv cc pin allows the intv cc power to be derived from a high efficiency external source such as one of the LTC3891 switching regulator outputs. the top mosfet driver is biased from the floating bootstrap capacitor, c b , which normally recharges during each cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one twelfth of the clock period every tenth cycle to allow c b to recharge. shutdown and start-up (run, track/ss pins) the LTC3891 can be shut down using the run pin. pulling this pin below 1.16v shuts down the main control loop. pulling the run pin below 0.7v disables the controller and most internal circuits, including the intv cc ldos. in this state, the LTC3891 draws only 14a of quiescent current. releasing the run pin allows a small internal current to pull up the pin to enable the controller. the run pin has a 7a pull-up which is designed to be large enough so that the run pin can be safely floated (to always enable the controller) without worry of condensation or other small board leakage pulling the pin down. this is ideal for always-on applications where the controller is enabled continuously and never shut down. the run pin may be externally pulled up or driven directly by logic. when driving the run pin with a low impedance source, do not exceed the absolute maximum rating of 8v. the run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage (for example, v in ), so long as the maximum current into the run pin does not exceed 100a. the run pin can also be implemented as a uvlo by connecting it to the output of an external resistor divider network off v in (see applications information section). the start-up of the controllers output voltage v out is controlled by the voltage on the track/ss pin. when the voltage on the track/ss pin is less than the 0.8v internal reference, the LTC3891 regulates the v fb voltage to the track/ss pin voltage instead of the 0.8v reference. this allows the track/ss pin to be used to program a soft-start by connecting an external capacitor from the track/ss pin to sgnd. an internal 10a pull-up current charges this capacitor creating a voltage ramp on the track/ss pin. as the track/ss voltage rises linearly from 0v to 0.8v (and beyond up to 5v), the output voltage v out rises smoothly from zero to its final value. alternatively the track/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the track/ss pin an external resistor divider from the other supply to ground (see applications information section).
LTC3891 12 3891fa light load current operation (burst mode operation, pulse-skipping or forced continuous mode) (pllin/mode pin) the LTC3891 can be enabled to enter high efficiency burst mode operation, constant frequency pulse-skipping mode, or forced continuous conduction mode at low load cur - rents. to select burst mode operation, tie the pllin/mode pin to sgnd. to select forced continuous operation, tie the pllin/mode pin to intv cc . to select pulse-skipping mode, tie the pllin/mode pin to a dc voltage greater than 1.2v and less than intv cc C 1.3v. when the controller is enabled for burst mode opera- tion, the minimum peak current in the inductor is set to approximately 25% of the maximum sense voltage even though the voltage on the ith pin indicates a lower value. if the average inductor current is higher than the load cur - rent, the error amplifier, ea, will decrease the voltage on the ith pin. when the ith voltage drops below 0.425v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. the ith pin is then disconnected from the output of the ea and parked at 0.450v. in sleep mode, much of the internal circuitry is turned off, reducing the quiescent current that the LTC3891 draws to only 50a. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the ith pin is reconnected to the output of the ea, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when the controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator, ir, turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from reversing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation or clocked by an external clock source to use the phase-locked loop (see frequency selection and phase-locked loop section), the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is deter - operation mined by the voltage on the ith pin, just as in normal operation. in this mode, the efficiency at light loads is lower than in burst mode operation. however, continu - ous operation has the advantage of lower output voltage ripple and less interference to audio circuitry. in forced continuous mode, the output ripple is independent of load current. when the pllin/mode pin is connected for pulse-skip - ping mode, the LTC3891 operates in pwm pulse-skipping mode at light loads. in this mode, constant frequency operation is maintained down to approximately 1% of designed maximum output current. at very light loads, the current comparator, icmp, may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade-off between efficiency and component size. low frequency opera- tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the LTC3891 can be selected using the freq pin. if the pllin/mode pin is not being driven by an external clock source, the freq pin can be tied to sgnd, tied to intv cc or programmed through an external resistor. tying freq to sgnd selects 350khz while tying freq to intv cc selects 535khz. placing a resistor between freq and sgnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 9. a phase-locked loop (pll) is available on the LTC3891 to synchronize the internal oscillator to an external clock source that is connected to the pllin/mode pin. the
LTC3891 13 3891fa LTC3891s phase detector adjusts the voltage (through an internal lowpass filter) of the vco input to align the turn-on of the controllers external top mosfet to the rising edge of the synchronizing signal. the vco input voltage is prebiased to the operating fre - quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency, the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clocks to the rising edge of tg. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency. the typical capture range of the phase-locked loop is from approximately 55khz to 900khz, with a guarantee to be between 75khz and 750khz. in other words, the LTC3891s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 750khz. the typical input clock thresholds on the pllin/mode pin are 1.6v (rising) and 1.2v (falling). output overvoltage protection an overvoltage comparator guards against transient over - shoots as well as other more serious conditions that may overvoltage the output. when the v fb pin rises by more than 10% above its regulation point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good pin the pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the v fb pin voltage is not within 10% of the 0.8v reference voltage. the pgood pin is also pulled low when the run pin is low (shut down). when the v fb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source no greater than 6v. foldback current when the output voltage falls to less than 70% of its nominal level, foldback current limiting is activated, pro - gressively lowering the peak current limit in proportion to the severity of the overcurrent or short-circuit condition. foldback current limiting is disabled during the soft-start interval (as long as the v fb voltage is keeping up with the track/ss voltage). operation
LTC3891 14 3891fa the typical application on the first page is a basic LTC3891 application circuit. LTC3891 can be configured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets and schottky diodes are selected. finally, input and output capacitors are selected. current limit programming the i lim pin is a tri-level logic input which sets the maximum current limit of the controller. when i lim is grounded, the maximum current limit threshold voltage of the current comparator is programmed to be 30mv. when i lim is floated, the maximum current limit threshold is 75mv. when i lim is tied to intv cc , the maximum current limit threshold is set to 50mv. sense + and sense C pins the sense + and sense C pins are the inputs to the cur - rent comparators. the common mode voltage range on these pins is 0v to 28v (abs max), enabling the LTC3891 to regulate output voltages up to a nominal 24v (allowing margin for tolerances and transients). the sense + pin is high impedance over the full common mode range, drawing at most 1a. this high impedance allows the current comparators to be used in inductor dcr sensing. the impedance of the sense C pin changes depending on the common mode voltage. when sense C is less than intv cc C 0.5v, a small current of less than 1a flows out of the pin. when sense C is above intv cc + 0.5v, a higher current (~700a) flows into the pin. between intv cc C 0.5v and intv cc + 0.5v, the current transitions from the smaller current to the higher current. applications information filter components mutual to the sense lines should be placed close to the LTC3891, and the sense lines should run close together to a kelvin connection underneath the current sense element (shown in figure 1). sensing cur - rent elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable. if inductor dcr sensing is used (figure 2b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. figure 1. sense lines placement with inductor or sense resistor c out to sense filter, next to the controller inductor or r sense 3891 f01 v in v in r sense intv cc boost tg sw bg place capacitor near sense pins sense + sense ? sgnd LTC3891 v out 3891 f02a *r1 and c1 are optional c1* r1* v in v in intv cc boost tg sw bg *place c1 near sense pins inductor dcrl sense + sense ? sgnd LTC3891 v out 3891 f02b r1 r2c1* (r1 || r2) ? c1 = l dcr r sense(eq) = dcr r2 r1 + r2 figure 2. current sensing methods (2b) using the inductor dcr to sense current (2a) using a resistor to sense current
LTC3891 15 3891fa low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the current comparator threshold voltage sets the peak of the induc - tor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, ? i l . to calculate the sense resistor value, use the equation: r sense = v sense(max) i max + d i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (30mv, 50mv or 75mv, depending on the state of the i lim pin). when using the controller in very low dropout conditions, the maximum output current level will be reduced due to the internal compensation required to meet stability criterion for buck regulators operating at greater than 50% duty factor. a curve is provided in the typical perfor - mance characteristics section to estimate this reduction in peak inductor current depending upon the operating duty factor. inductor dcr sensing for applications requiring the highest possible efficiency at high load currents, the LTC3891 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor represents the small amount of dc resistance of the copper wire, which can be less than 1m for todays low value, high current inductors. in a high current application requiring such an inductor, power loss through a sense resistor would cost several points of efficiency compared to inductor dcr sensing. if the external (r1||r2) ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external filter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the inductor value calculation section, the target sense resistor value is: r sense(equiv) = v sense(max) i max + d i l 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (30mv, 50mv or 75mv, depending on the state of the i lim pin). next, determine the dcr of the inductor. when provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coefficient of copper resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value (r d ), use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0.1f to 0.47f. this forces r1 || r2 to around 2k, reducing error that might have been caused by the sense + pins 1a current. applications information
LTC3891 16 3891fa the equivalent resistance r1 || r2 is scaled to the tem - perature inductance and maximum dcr: r1|| r2 = l dcr at 20 c ( ) ? c1 the sense resistor values are: r1 = r1|| r2 r d ; r2 = r1 ? r d 1C r d the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) C v out ( ) ? v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc - tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. inductor value calculation the operating frequency and inductor selection are inter - related n that higher operating frequencies allow the use of smaller inductor and capacitor values. so why would anyone ever choose to operate at lower frequencies with larger components? the answer is efficiency. a higher frequency generally results in lower efficiency because of mosfet switching and gate charge losses. in addi - tion to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current, ? i l , decreases with higher inductance or higher frequency and increases with higher v in : i l = 1 f ( ) l ( ) v out 1? v out v in ? ? ? ? ? ? accepting larger values of ? i l allows the use of low in - ductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ? i l = 0.3(i max ). the maximum ? i l occurs at the maximum input voltage. the inductor value also has secondary effects. the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher ? i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! applications information
LTC3891 17 3891fa power mosfet and schottky diode (optional) selection two external power mosfets must be selected for the LTC3891 controller: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5.1v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. pay close attention to the bv dss specification for the mosfets as well. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers datasheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i max ( ) 2 1+ ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc ? v thmin + 1 v thmin ? ? ? ? ? ? f ( ) p sync = v in ? v out v in i max ( ) 2 1+ ( ) r ds(on) applications information where is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfets miller threshold voltage. v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1+ ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. a schottky diode can be inserted in parallel with the bot - tom mosfet to conduct during the dead-time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out selection the selection of c in is usually based off the worst-case rms input current. the highest (v out )(i out ) product needs to be used in the formula shown in equation 1 to determine the maximum rms capacitor current requirement. in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the
LTC3891 18 3891fa applications information maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/ 2 (1) this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the LTC3891, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the LTC3891, is also suggested. a small (10) resistor placed between c in (c1) and the v in pin provides further isolation. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( ? v out ) is approximated by: v out i l esr + 1 8 ? f ? c out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and ? i l is the ripple current in the inductor. the output ripple is highest at maximum input voltage since ? i l increases with input voltage. setting output voltage the LTC3891 output voltage is set by an external feed - back resistor divider carefully placed across the output, as shown in figure 3. the regulated output voltage is determined by: v out = 0.8v 1 + r b r a ? ? ? ? ? ? to improve the frequency response, a feedforward ca - pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. run pin the LTC3891 is enabled using the run pin. it has a rising threshold of 1.21v with 50mv of hysteresis. pulling the run pin below 1.16v shuts down the main control loop. pulling it below 0.7v disables the controller and most internal circuits, including the intv cc ldos. in this state, the LTC3891 draws only 14a of quiescent current. releasing the run pin allows a small 7a internal current to pull up the pin to enable the controller. the run pin may be externally pulled up or driven directly by logic. when driving the run pin with a low impedance source, do not exceed the absolute maximum rating of 8v. the run pin has an internal 11v voltage clamp that allows the run pin to be connected through a resistor to a higher voltage (for example, v in ), so long as the maximum current into the run pin does not exceed 100a. the run pin can be implemented as a uvlo by connecting it to the output of an external resistor divider network off v in , as shown in figure 4. LTC3891 v fb v out r b c ff r a 3891 f03 figure 3. setting output voltage LTC3891 run v in r b r a 3891 f04 figure 4. using the run pin as a uvlo
LTC3891 19 3891fa the rising and falling uvlo thresholds are calculated using the run pin thresholds: v uvlo(rising) = 1.21v 1 + r b r a ? ? ? ? ? ? v uvlo(falling) = 1.16v 1 + r b r a ? ? ? ? ? ? the resistor values should be carefully chosen such that the absolute maximum ratings of the run pin do not get violated over the entire v in voltage range. tracking and soft-start (track/ss pin) the start-up of v out is controlled by the voltage on the track/ss pin. when the voltage on the track/ss pin is less than the internal 0.8v reference, the LTC3891 regulates the v fb pin voltage to the voltage on the track/ss pin instead of 0.8v. the track/ss pin can be used to program an external soft-start function or to allow v out to track another supply during start-up. soft-start is enabled by simply connecting a capacitor from the track/ss pin to ground, as shown in figure 5. an internal 10a current source charges the capacitor, providing a linear ramping voltage at the track/ss pin. the LTC3891 will regulate the v fb pin (and hence v out ) according to the voltage on the track/ss pin, allowing v out to rise smoothly from 0v to its final regulated value. the total soft-start time will be approximately: t ss = c ss ? 0.8v 10a applications information pin of the slave supply (v out ), as shown in figure 7. during start-up v out will track v x according to the ratio set by the resistor divider: v x v out = r a r tracka ? r tracka + r trackb r a + r b for coincident tracking (v out = v x during start-up): r a = r tracka r b = r trackb figure 5. using the track/ss pin to program soft-start LTC3891 track/ss c ss sgnd 3891 f05 alternatively, the track/ss pin can be used to track another supply during start-up, as shown qualitatively in figures 6a and 6b. to do this, a resistor divider should be connected from the master supply (v x ) to the track/ss time v x(master) v out(slave) output voltage 3891 f06a time 3891 f06b v x(master) v out(slave) output voltage (6a) coincident tracking (6b) ratiometric tracking figure 6. two different modes of output voltage tracking LTC3891 v out v x v fb track/ss 3891 f07 r b r a r tracka r trackb figure 7. using the track/ss pin for tracking
LTC3891 20 3891fa intv cc regulators the LTC3891 features two separate internal p-channel low dropout linear regulators (ldo) that supply power at the intv cc pin from either the v in supply pin or the extv cc pin depending on the connection of the extv cc pin. intv cc powers the gate drivers and much of the LTC3891s internal circuitry. the v in ldo and the extv cc ldo regulate intv cc to 5.1v. each of these can supply a peak current of at least 50ma and must be bypassed to ground with a minimum of 2.2f ceramic capacitor. no matter what type of bulk capacitor is used, an additional 1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3891 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the v in ldo or the extv cc ldo. when the voltage on the extv cc pin is less than 4.7v, the v in ldo is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the LTC3891 intv cc current is limited to less than 32ma from a 40v supply when not using the extv cc supply at a 70c ambient temperature: t j = 70c + (32ma)(40v)(43c/w for qfn) = 125c to prevent the maximum junction temperature from be - ing exceeded, the input supply current must be checked while operating in forced continuous mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above 4.7v, the v in ldo is turned off and the extv cc ldo is enabled. the extv cc ldo remains on as long as the voltage applied to extv cc remains above 4.5v. the extv cc ldo attempts to regulate the intv cc voltage to 5.1v, so while extv cc is less than 5.1v, the ldo is in dropout and the intv cc voltage is approximately equal to extv cc . when extv cc is greater than 5.1v, up to an absolute maximum of 14v, intv cc is regulated to 5.1v. using the extv cc ldo allows the mosfet driver and control power to be derived from one of the LTC3891s switching regulator outputs (4.7v v out 14v) during normal operation and from the v in ldo when the output is out of regulation (e.g., start-up, short-circuit). if more current is required through the extv cc ldo than is specified, an external schottky diode can be added between the extv cc and intv cc pins. in this case, do not apply more than 6v to the extv cc pin and make sure that extv cc v in . significant efficiency and thermal gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). for 5v to 14v regulator outputs, this means connecting the extv cc pin directly to v out . tying the extv cc pin to an 8.5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (32ma)(8.5v)(43c/w) = 82c however, for 3.3v and other low voltage outputs, addi - tional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc grounded. this will cause intv cc to be powered from the internal 5.1v regulator resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v to 14v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if an external supply is available in the 5v to 14v range, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. ensure that extv cc < v in . applications information
LTC3891 21 3891fa 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. this can be done with the capacitive charge pump shown in figure 8. ensure that extv cc < v in . applications information topside mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate-source of the mosfet. this enhances the top mosfet switch and turns it on. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the top - side mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. extv cc v in tg sw bg pgnd LTC3891 r sense v out nds7002 c out 3891 f08 mbot mtop c in l bat85 bat85 bat85 figure 8. capacitive charge pump for extv cc fault conditions: current limit and current foldback the LTC3891 includes current foldback to help limit load current when the output is shorted to ground. if the output voltage falls below 70% of its nominal output level, then the maximum sense voltage is progressively lowered from 100% to 45% of its maximum selected value. under short- circuit conditions with very low duty cycles, the LTC3891 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dis - sipating most of the power but less than in normal opera - tion. the short-circuit ripple current is determined by the minimum on-time, t on(min) , of the LTC3891 (95ns), the input voltage and inductor value: i l(sc) = t on(min) v in l ? ? ? ? ? ? the resulting average short-circuit current is: i sc = 45% ? i lim(max) C 1 2 d i l(sc) fault conditions: overvoltage protection (crowbar) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. the crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top mosfet if the short occurs while the control - ler is operating. a comparator monitors the output for overvoltage condi - tions. the comparator detects faults greater than 10% above the nominal output voltage. when this condition is sensed, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the overvoltage condition persists; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse. the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage.
LTC3891 22 3891fa phase-locked loop and frequency synchronization the LTC3891 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter, and a voltage-controlled oscillator (vco). this allows the turn-on of the top mosfet to be locked to the rising edge of an external clock signal applied to the pllin/mode pin. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the vco input. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the vco input. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the internal filter capacitor, clp, holds the voltage at the vco input. note that the LTC3891 can only be synchronized to an external clock whose frequency is within range of the LTC3891s internal vco, which is nominally 55khz to 900khz. this is guaranteed to be between 75khz and 750khz. typi - cally, the external clock (on the pllin/mode pin) input high threshold is 1.6v, while the input low threshold is 1.1v. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchro - nization frequency. the vcos input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin. once prebiased, the pll only needs to adjust applications information the frequency slightly to achieve phase lock and synchro- nization. although it is not required that the free-running frequency be near external clock frequency, doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. table 2 summarizes the different states in which the freq pin can be used. table 2 freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor dc voltage 50khz to 900khz any of the above external clock phase locked to external clock minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the LTC3891 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 3891 f09 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 figure 9. relationship between oscillator frequency and resistor value at the freq pin
LTC3891 23 3891fa charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in f ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTC3891 is approximately 95ns. however, as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns. this is of particular concern in forced continuous applica - tions with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with cor - respondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3891 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typically results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power applications information mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying intv cc from an output-derived source power through extv cc will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(efficiency). for example, in a 20v to 5v applica - tion, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the midcurrent loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resis - tor and input and output capacitor esr. in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resis - tances of l, r sense and esr to obtain i 2 r losses. for example, if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m (sum of both input and output capacitance losses), then the total resistance is 130m. this results in losses ranging from 3% to 13% as the output current increases from 1a to 5a for a 5v output, or a 4% to 20% loss for a 3.3v output. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7) ? v in ? 2 ? i o(max) ? c rss ? f
LTC3891 24 3891fa applications information other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses including body diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ? i load (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recov - ery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the availability of the ith pin not only allows optimization of control loop behavior, but it also provides a dc coupled and ac filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the ith external components shown in figure 10 circuit will provide an adequate starting point for most applications. the ith series rc-cc filter sets the dominant pole-zero loop compensation. the values can be modified slightly to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing rc and the bandwidth of the loop will be increased by de - creasing cc. if rc is increased by the same factor that cc is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. design example as a design example, assume v in = 12v (nominal), v in = 22v (max), v out = 3.3v, i max = 5a, v sense(max) = 75mv and f = 350khz. the inductance value is chosen first based on a 30% ripple current
LTC3891 25 3891fa applications information assumption. the highest value of ripple current occurs at the maximum input voltage. tie the freq pin to gnd, generating 350khz operation. the minimum inductance for 30% ripple current is: i l = v out f ( ) l ( ) 1? v out v in(nom) ? ? ? ? ? ? ? ? a 4.7h inductor will produce 29% ripple current. the peak inductor current will be the maximum dc value plus one half the ripple current, or 5.73a. increasing the ripple current will also help ensure that the minimum on-time of 95ns is not violated. the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) f ( ) = 3.3v 22v 350khz ( ) = 429ns the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (64mv): r sense 64mv 5.73a 0.01 ? choosing 1% resistors: r a = 25k and r b = 78.7k yields an output voltage of 3.32v. the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p main = 3.3v 22v 5a ( ) 2 1+ 0.005 ( ) 50 c C 25 c ( ) ? ? ? ? 0.035 ? ( ) + 22v ( ) 2 5a 2 2.5 ? ( ) 215pf ( ) ? 1 5v C 2.3v + 1 2.3v ? ? ? ? ? ? 350khz ( ) = 331mw a short-circuit to ground will result in a folded back cur - rent of: i sc = 34mv 0.01 ? C 1 2 95ns 22v ( ) 4.7h ? ? ? ? ? ? ? ? = 3.18a with a typical value of r ds(on) and = (0.005/c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p sync = 3.28a ( ) 2 1.125 ( ) 0.022 ? ( ) = 250mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approxi - mately: v oripple = r esr (di l ) = 0.02(1.45a) = 29mv p-p pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. check the following in your layout: 1. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter - minals. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 2. does the LTC3891 v fb pins resistive divider connect to the (+) terminal of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground. the feedback resistor connections should not be along the high current input feeds from the input capacitor(s).
LTC3891 26 3891fa applications information 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 4. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers cur - rent peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. 5. keep the sw, tg, and boost nodes away from sensitive small-signal nodes. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC3891 and occupy minimum pc trace area. 6. use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be main- tained over the input voltage range down to dropout and until the output load drops below the low current opera - tion thresholdtypically 25% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. an embarrassing problem, which can be missed in an otherwise properly working switching regulator, results when the current sensing leads are hooked up backwards. the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. compensation of the voltage loop will be much more sensitive to component selection. this behavior can be investigated by temporarily shorting out the current sensing resistordont worry, the regulator will still maintain control of the output voltage.
LTC3891 27 3891fa applications information v in c in c out v pull-up r out c intvcc m1 pgood 1f ceramic l1 v out 3891 f10 r sense sense ? sense + v fb ith extv cc intv cc bg boost sw tg pgood LTC3891 track/ss freq pllin/mode sgnd sgnd run *r1, c1 and d1 are optional r1* c1* m2 d1* + + i lim v in pgnd gnd r l1 d1 l1 sw r sense v out c out v in c in r in bold lines indicate high switching current. keep lines to a minimum length. 3891 f11 figure 10. recommended printed circuit layout diagram figure 11. branch current waveforms
LTC3891 28 3891fa figure 12. high efficiency 3.3v step-down converter 0.1f c in 22f v in 4v to 60v intv cc 41.2k 10k 2200pf 100k 100k 31.6k 3891 f12 2.2f d1 100pf 0.1f freq ith sgnd sgnd LTC3891 v in pgood run i lim extv cc pllin/mode intv cc pgnd l1 4.7h r sense 8m boost sw bg sense + sense ? v fb tg mtop mbot 1nf c out 150f v out 3.3v 5a track/ss mtop, mbot: si7850dp l1 coilcraft ser1360-472kl c out : sanyo 6tpe470m d1: dfls1100 figure 13. high efficiency 12v step-down converter 0.1f c in 22f v in 12.5v to 60v v out intv cc 34.8k 470pf 100k 100k mtop, mbot: bsc100n06ls3 l1 coilcraft ser1360-802kl c out : sanyo 16svp180mx d1: dfls1100 6.98k 3891 f13 2.2f d1 100pf 0.1f freq ith sgnd sgnd LTC3891 v in pgood run i lim extv cc pllin/mode intv cc pgnd l1 8h r sense 9m boost sw bg sense + sense ? v fb tg mtop mbot 1nf c out 180f v out 12v 3a track/ss applications information
LTC3891 29 3891fa package description 3.00 0.10 1.50 ref 4.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or 0.25 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (udc20) qfn 1106 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.50 ref 3.10 0.05 4.50 0.05 1.50 ref 2.10 0.05 3.50 0.05 package outline r = 0.05 typ 1.65 0.10 2.65 0.10 1.65 0.05 2.65 0.05 0.50 bsc udc package 20-lead plastic qfn (3mm 4mm) (reference ltc dwg # 05-08-1742 rev ?) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LTC3891 30 3891fa package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. fe20 (cb) tssop rev i 0211 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation cb
LTC3891 31 3891fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 10/12 added intv cc to absolute maximum ratings updated fe package 2 30
LTC3891 32 3891fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 1012 rev a ? printed in usa related parts typical application part number description comments ltc3890/ltc3890-1 60v, low i q , dual output 2-phase synchronous step- down dc/dc controller phase-lockable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3857/ltc3857-1 low i q , dual output 2-phase synchronous step-down dc/dc controllers with 99% duty cycle phase-lockable fixed frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a ltc3858/ltc3858-1 low i q , dual output 2-phase synchronous step-down dc/dc controllers with 99% duty cycle phase-lockable fixed frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 170a ltc3868/ltc3868-1 low i q , dual output 2-phase synchronous step-down dc/dc controller with 99% duty cycle phase-lockable fixed frequency 50khz to 900khz, 4v v in 24v, 0.8v v out 14v, i q = 170a ltc3834/ltc3834-1 low i q , single output synchronous step-down dc/dc controller with 99% duty cycle phase-lockable fixed frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 30a ltc3835/ltc3835-1 low i q , single output synchronous step-down dc/dc controller with 99% duty cycle phase-lockable fixed frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 80a lt3845a 60v, low i q , single output synchronous step-down dc/dc controller adjustable fixed frequency 100khz to 500khz, 4v v in 60v, 1.23v v out 36v, i q = 120a ltc3859 low i q , triple output buck/buck/boost synchronous dc/dc controller outputs 4v remain in regulation through cold crank, 2.5v v in 38v, v out(bucks) up to 24v, v out(boost) up to 60v, i q = 55a ltc3824 low i q , single output step-down controller, 100% duty cycle fixed 200khz to 600khz, 4v v in 60v, 0.8v v out v in , i q = 40a, msop-10e 0.1f c in 22f v in 9v to 60v v out intv cc 34.8k 470pf 100k 100k mtop, mbot: si7850dp l1 coilcraft ser1360-802kl c out : sanyo 10tpe330m d1: dfls1100 10.5k 3891 f14 2.2f d1 0.1f freq ith sgnd sgnd LTC3891 v in pgood run i lim extv cc pllin/mode intv cc pgnd l1 8h r sense 10m boost sw bg sense + sense ? v fb tg mtop mbot 1nf c out 330f v out 8.5v 3a track/ss figure 14. high efficiency 8.5v step-down converter

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